VLSI Design Projects 2015

08/08/2015 Other Classes

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Nxtlogic is a leading software provider in India. We currently involved in the web application development, web designing, web hosting, mobile application development, mobile hosting, final year projects and SEO.   Latest 2015-16 VLSI Projects: Here we are providing a list of latest IEEE 2015 VLSI project titles. Students, who want to get training from the list of project, can contact us. We have a well-versed developers and trainers. These projects consist of full project report, source code, and paper presentation. Your new innovative ideas also we appreciate and developing. For more projects reference kindly visit our website – http://www.nxtproject.com/                                                             VLSI stands for “Very Large Scale Integration”. Generally there are mainly two types of VLSI projects we can develop. 1 Projects in VLSI based System Design Projects in VLSI based system design are the projects which involve the design of various types of digital systems that can be implemented on a PLD device like a FPGA or a CPLD. 2 VLSI Design Projects The projects which deal with the semiconductor design are called as Projects in VLSI design. These are very difficult and expensive to implement in real time.   VLSI IEEE BASED PROJECT TITLES 2015 -16 1. An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability 2. Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications 3. Recursive Approach to the Design of a Parallel Self-Timed Adder 4. Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing 5. Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block 6. Exploiting Same Tag Bits to Improve the Reliability of the Cache Memories 7. Fault Tolerant Parallel Filters Based on Error Correction Codes 8. Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations 9. Z-TCAM: An SRAM-based Architecture for TCAM 10. Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic 11. Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line 12. Diagnosis and Layout Aware (DLA) Scan Chain Stitching 13. A 3.6-mW 50-MHz PN Code Acquisition Filter via Statistical Error Compensation in 180-nm CMOS 14. Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test Set An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis 15. Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop 16. A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator 17. Fine-Grained Fast Field-Programmable Gate Array Scrubbing 18. Design of Efficient Content Addressable Memories in High-Performance FinFET Technology 19. A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist 20. A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT 21. A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes 22. Variable Latency Speculative Han-Carlson Adder 23. Low-Power and Area-Efficient Shift Register Using Pulsed Latches 24. Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications 25. Code Compression for Embedded Systems Using Separated Dictionaries 26. Design for Testability of Sleep Convention Logic 27. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels 28. WCET-Aware Energy-Efficient Data Allocation on Scratchpad Memory for Real-Time Embedded Systems 29. Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic 30. Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks 31. An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating 32. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication 33. Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames 34. A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies 35. In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers 36. A Novel Quantum-Dot Cellular Automata X-bit ×32-bit SRAM 37.Reliable and Error Detection Architectures of Pomaranch for False-Alarm-Sensitive Cryptographic Applications 38. A High-Speed FPGA Implementation of an RSD-Based ECC Processor 39. Scalable Elliptic Curve Cryptosystem FPGA Processor for NIST Prime Curves 40. A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell 41. VLSI-Assisted Nonrigid Registration Using Modified Demons Algorithm 42. A Relative Imaging CMOS Image Sensor for High Dynamic Range and High Frame-Rate Machine Vision Imaging Applications 43. High-Density and High-Reliability Nonvolatile Field-Programmable Gate Array With Stacked 1D2R RRAM Array 44. A Novel Thyristor-Based Silicon Physical Unclonable Function 45. A definition of the number of detections for faults with single tests in a compact scan-based test set

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